The present invention relates to integrated circuits, and more specifically, to through-silicon vias (TSVs) formed through an n+ epitaxy layer which reduces parasitic capacitance.
In integrated circuit technology, TSVs are used to create a vertical electrical connection (e.g., a via) passing completely through a silicon wafer or die, and can be used to connect integrated circuits together. FIG. 1 is an example of a TSV in a semiconductor device in the conventional art. As shown in FIG. 1, a semiconductor device 10 includes a semiconductor substrate 12 formed of a low dopant concentration (e.g., a p− layer) and having a device layer 14 formed on a top surface thereof. A trench 16 is etched through the substrate 12 to form a TSV and a dielectric layer 18 is deposited within the trench 16 to form a liner along sidewalls surfaces of the trench 16 for isolation purposes. The trench 16 is then filled with a conductive layer to form a TSV conductor 19.
FIG. 2 is another example of a TSV in a semiconductor device in the conventional art. As shown in FIG. 2, the semiconductor device 20 includes a semiconductor substrate 22 having an n+ epitaxy layer 23 formed thereon and a device layer 24 formed on the n+ epitaxy layer 23. A trench 26 is etched through the substrate 22 and a dielectric layer 18 is deposited within the trench 26 to form a liner along sidewall surfaces of the trench 26. The trench 26 is then filled with a conductive layer to form a TSV conductor 29.
In both examples shown in FIGS. 1 and 2, a MOS (metal oxide semiconductor) capacitor is formed. There may be several problems associated with the MOS capacitors when a n+ epitaxy layer is included as shown in FIG. 2. One of the problems includes capacitance issues. FIG. 3 is a diagram illustrating capacitance vs. gate voltage regarding the TSVs shown in FIGS. 1 and 2. As shown in FIG. 3, for voltages placed on the TSV conductor 19 (as represented by line 32) such as zero or a positive voltage, the capacitance per unit area is very low for example, approximately 1×10−8 F/cm2. On the other hand, when voltage is placed on the TSV conductor 29 (as represented by line 34), there is a significant increase in the capacitance with the inversion (as represented by arrow 36). Furthermore, when the TSV capacitor operates in the inversion mode, it introduces significant voltage and frequency dependence that thus complicates the TSV modeling.
In eDRAM (i.e., embedded capacitor-based dynamic random access memory) technology, it is necessary to have the n+ epitaxy layer but when combined with the TSV, capacitance significantly increases as shown in FIG. 3.